Beacon target selector and evaluator

ABSTRACT

An IFF target evaluator comprising signal-storage means consisting of a plurality of series-connected shift registers each of whose outputs are also connected to a different level of a Pascal-triangle configuration of AND and OR gates used as a decoding means. The outputs of the decoding means show whether a series of consecutive pulse positions contain enough pulses to indicate a target; how many consecutive &#39;&#39;&#39;&#39;ones&#39;&#39;&#39;&#39; have been received from a predetermined number of range sweeps; and how many consecutive &#39;&#39;&#39;&#39;zeros&#39;&#39;&#39;&#39; have been received.

United States Patent 11 1 1111 3,781,881 Hovey Dec. 25, 1973 BEACONTARGET SELECTOR AND EVALUATOR Primary Examiner-T. H. Tubbesing [75]Inventor: John M. Hovey, Oxon Hill, Md. Attmey R' sclascla et [73]Assignee: The United States of America as represented by the Secretaryof the [57] ABSTRACT Navy, Washington, DC. An [FF target evaluatorcomprising signal-storage means consisting of a plurality ofseries-connected [22] filed July 1972 shift registers each of whoseoutputs are also con- [21] Appl. No.: 273,912 nected to a differentlevel of a Pascal-triangle configuration of AND and OR gates used as adecoding means. The outputs of the decoding means show 343/6'5 gi ggwhether a series of consecutive pulse positions contain 58] Field DP 6 Renough pulses to indicate a target; how many consecutive ones have beenreceived from a predetermined numb r 0 ran e swee snd how manconsecutive Reierences Clted f g P 1 a Y zeros have been received.UNITED STATES PATENTS 3,412,397 11/1968 Evans 343/5 01 5 Clams, 1 DrawmgFigure BUS'I ['02 l 0 our-11 W54 lNv-l l our-1o SR-l O 0 I0 I l l AG AGI04 ouT-2o OUTZI BUS-3 I 0 c1 0 1 NV-3 I 100010 01110 e 1 e a 0 O 0 I 0our- -'"OUT-3I SR 3 BUS-4 I o o 1 o INV:4

OUT- OUT 4| SR4 BUS-5 I mv s 2o 21 22 22- 24 2s 2s 27 our-- 0ur-51 SW5BUS-6 INV-VG 03132 3334 as 37 as E9 AND GATE 1 our-s1 Q? 11 12 14 OR"GATE LEGEND OUT-O OUT-l OUT-2 OUT-3 OUT-4 OUT-5 OUT-G 1 BEACON TARGETSELECTOR AND EVALUATOR BACKGROUND OF THE INVENTION This inventionrelates to beacon systems and especially to an improved circuit foridentifying friendly targets in an beacon system.

The solution to the problem of sensing and identifying (classifying)targets in beacon systems in general and particularly in military IFF(Identification Friend or Foe) systems, such as the Mark XII IFF system,has been pursued for a number of years. Some evaluators have beendeveloped as demonstration devices and a very complex "all targetevaluator was built for use in SAGE (Semi-Automatic Ground Equipment).All units that have been developed thus far have been very complex,bulky and expensive and some have not been based on valid statisticalcriteria.

SUMMARY OF THE INVENTION OBJECTS An object of the invention is to senseand evaluate targets for a beacon system.

Another object is to provide an IFF target evaluator which is relativelysimple and small in structure and inexpensive.

Other objects, advantages and novel features of the invention willbecome apparent from the following detailed description of the inventionwhen considered in conjunction with the accompanying drawing wherein:

BRIEF DESCRIPTION OF THE DRAWING The single FIGURE illustrates anembodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION In general, the inventioncomprises a storage means which receives target signal returns from IFFinterrogations and a decoding means for evaluating the return signals.The decoding means receives the outputs of the storage means as part ofits input signals. (An interrogation period is considered to beequivalent in time, for example, to the time required for a PPI radialsweep where the PP] indicator is being used in the IFF system to providea visual display of targets.)

The storage means may comprise a plurality of shift registers 100 (seeFIG.) in series with each other. (For the purpose of simplicity ofillustration and explanation, only five registers are shown. However,any number can be used.) The shift registers are multi-stages (or bitpositions) clocked at a l Ml-Iz rate. Each registertherefore providesI000 usec of storage with a granularity of l psec. The clock (not shown)which drives the registers is enabled coincident with each interrogationand runs for I000 counts. The output from the last stage of eachregister appears on its associated bus;

thus, the output of SR-l appears on Bus-2. (It should be noted that theoperation of the storage registers chops the interrogation period intoI00 smaller periods of l usec each. Each smaller period corresponds to adistance (actually a small range of distances) and therefore eachshift-register stage or position is sometimes called a range bin.)

The wideo signals derived in the course of each interrogation areentered into SR-l at Video Input" and are shifted along to a position inthe register (range bin) corresponding to the range of the target, whenthe register is full (the interrogation is complete). At the start ofthe next interrogation, the output of the last stage of SR-l, whichappears on Bus-2, is shifted into the first stage of SR-2. At the end ofthe second interrogation, all the information received from the firstinterrogation is in the register SR-Z and all received from the secondinterrogation is in SR-l, with corresponding bit positions, or stages,in each register containing information from the same range. Thiscontinues until at the end of the fifth interrogation, all theinformation received from che first interrogation is in SR-S. Note thatthe time of entry of any bit will determine its final position in theregisters. For example, information received during the one-hundredthmicrosecond following an interrogation will finally appear in the stagewhich is one hundred stages from the last stage in the shift register.

As reply video from any interrogation arrives at Video Input, it isloaded into SR-l and also applied to Bus-l. Video from previousinterrogations that was received at the same relative time in eachinterrogation period appears at Bus'2 through Bus-5 simultaneously. Itmay be seen that if replies to six consecutive interrogations werereceived from an aircraft at a range of approximately 8 miles, eachregister would contain a reply bit in stage and that, as the reply bitto the sixth interrogation is received, corresponding bits from thepreceding five interrogations are all available in parallel on theshift-register output busses. At this instant, a parallel logicoperation can be performed to determine certain characteristics of thereturn signals. The results can be read out and display at the appropriate range and azimuth on an associated display means.

The means for evaluating the data in the storage registers is thedecoding means which is in essence, and electronic embodiment of Pascalstriangle. (Hereinafter the term Pascal-triangle decoding means will beunderstood to be the decoder circuit which is described below.) Thedecoder consists of a level of AND and OR-gates, 104 and 106respectively, for each shift register. Thus, in the present embodiment,there are five shift registers and five levels in the decoder. The firstlevel has four AND gates (AG-l, AG-2, AG-3 and AG-4) and one OR-gate(OG-l). Each level adds two AND-gates and one OR-gate so that level twohas six AND-gates and two OR-gates, level three has eight AND-gates andthree OR-gates, and so on.

In the triangle, the outputs of the two outer AND- gates (one on eachside) is fed directly to the next lower level, whereas the innerAND-gates are formed into pairs, the output of each pair being fed to adifferent OR-gate before being fed to the next lower level. Thus, theoutputs of AG-l and AG-4 go directly to the second level but the outputsof AG-2 and AG-3 are fed as a pair to 06-1 and its output goes to leveltwo. The number of OR-gates can be found from the formula (OR-gates)(AND-gates) 2/2 The input to each level of the decoder can be consideredto be of two types: first, a stored input from its associated registerconsisting of the output from the last stage of the register which is onthe Bus and, second, the inverted signal from the Bus since each Bussignal is also applied to its associated inverter 102. (Thus, the signalon Bus-4 is applied to the input of lNV-4 (invert- TABLE 1 InputsOutputs 7 From from No. No. From Upper Each Level AND OR Storage LevelLevel Gates Gates l 4 l 2 2 3 2 6 2 2 3 4 3 8 3 2 4 5 4 l 4 2 S 6 l2 5 26 7 Table I gives some interesting figures which provide information asto the structure of the decoder. The first level has four AND-gates andeach lower level thereafter has two more AND-gates than the one aboveit. For input purposes, the AND-gates are separated into pairs (inputpairs) starting from the left side of each level, the Bus signal goingto one gate in each pair and the inverted signal going to the other gatein ech pair. The inner AND-gates (excluding the first and last AND-gates such as AG-S and AG-lll) on each level are again arranged in pairs(output pairs), the output of each pair being coupled to a differentOR-gate. Thus, on level 2, AG-S and 6, AG-7 and 8, AG-9 and 10 forminput pairs while AG-6 and 7, AG-S and 9 form output pairs. Output pairAG-6 and 7 is coupled to 06-2 and output pair AG-8 and 9 is coupled to00-3. The outputs from level 2 therefore consist of the outputs of theend AND-gates AG-S and AG-lO and the outputs of the level-2 OR- gates06-2 and 06-3.

The inputs to each level also include the outputs of the level above(but, in the case of level 1, these would be the Bus-l or Video Inputsignal and the inverted Bus-1 signal). Each of these inputs is appliedto both AND GATES IN A DIFFERENT INPUT PAIR, IN ORDER. Thus, the outputfrom AG-l is applied to the level-2 input pair 06-5 and 6, the outputfrom 06-1 is applied to the level-2 input pair ACE-'7 and 8, and theoutput from ACE-4 is applied to the level-2 input pair AG-9 and 10.

The outputs of the decoder are of different types depending on whichside of the triangle they are taken from. Thus, the outputs along thebase of the triangle indicate how many of the last six bits contained alogical one (assuming that a target return is a one signal and a lack oftarget return is a zero signal). Thus, if there were two ones in thelast six bits, there would be a signal (a one) at OUT-2; if there were 5ones in the last six bits, there would be a signal at OUT-5; etc. Thiscan be termed m out of n occurrence detection, in being the number oftrue bits (or ones) (n can equal any number from zero to n) and n beingthe number of bit positions in the logical word which is beingconsidered (n is also equal to the number of shift registers 6 signalfor OG-8 provides an indication that there have been 2 ones in the last5 bits.

For the evaluation of signal returns, a decision is made in accordancewith various factors, such as signal interference level, false alarmtolerance, etc., as to how many one signals in how many bits will betaken to indicate a signal. Thus, it may be decided that four ones inseven bits are necessary and the decoder would be built with six levels,OUT-4 then being connected to the altering or display circuits. in outof n detection can also be applied to obtain the statisticaldistribution curves of incoming signals.

The outputs taken from the right-end AND-gates on each level indicateruns of ones, i.e., how many consecutive ones (or target returns) therehave been. This is important when it is necessary to decide whether atarget return is starting to be received. Thus, OUT-41 would provide aone signal when four consecutive ones are received.

The outputs taken from the left-end AND-gates on each level indicateruns of zeroes, i.e., how many consecutive zeros there have been. Thisis important in the decision as to whether a given target hasdisappeared (whether signal returns from it have ended). Thus, OUT-20would provide a one signal when two consecutive zeroes are received.

The invention is of course used with receiving and signal utilization ordisplay circuits.

A short example of how the decoder operates will now be given. Let theVideo Input, or Bus-l signal, be a one; then the output oflNV-l is azero. Let the simultaneous signal output of SR-l be a one; then thesignal on BUS-2 is a one and the signal from [NV-2 is a zero. The inputsto AG-l, 2, 3 and 4 are 00, 01, 01 and 11, respectively. OUT-20 is then0, the outputs of AG-2 and 3 are 0, and OUT-21 is a I. Now suppose thesame previous conditions and an output of 0 on BUS-3. The output oflNV-3 is a 1. The inputs to AG-5, 6, 7, 8, 9 and 10 are 10, 00, 10, 00,11 and 10, respectively. OUT-30 is a 0, OUT-31 is a 0, and the outputsfrom AG-6, 7, 8 and 9 are 0, 0, 0 and 1, respectively. The outputs from06-2 and 3 are 0 and 1, respectively. Since the output from 06-3 is the2 out of 3 output a 1 from 06-3 indicates that there have been two onesin the last three bits.

Obviously many modifications and variations of the present invention arepossible in light of the above teachings. It is therefore to beunderstood that within the scope of the appended claims the inventionmay be practiced otherwise than as specifically described.

What is claimed and desired to be secured by Letters Patent of theUnited States is:

l. A target-identifying circuit for use in beacon systems comprising:

storage means for chopping each interrogation period into a plurality ofsmall range-bin periods and for providing a plurality of simultaneousoutputs for each range-bin period comprising the signal received forthat range-bin period during the immediate interrogation and apredetermined number of previous interrogations, said simultaneousoutputs being derived in order for each range-bin period in theinterrogation period and the whole process being repeated for eachinterrogation period; and decoding means arranged in the form of aPascals triangle for classifying the incoming video signals by anm-out-of n classification where n is the predetermined number of bitpositions in the word to be analyzed, corresponding to the number ofsimultaneous storage means outputs plus one, and m is the number of truebits which occur in the word,

register output and the outputs of the level above it, except that thefirst or topmost level has as inputs the incoming video signal and itsinverse in place of the outputs of the level above it,

corresponding to a number from zero to n. 5

2. A circuit as in claim 1, further providing outputs indicating runs ofconsecutive logical ones in the incoming and stored video signals.

3. A circuit as in claim 1, further providing outputs indicating runs oflogical consecutive zeros in the in- 10 coming and stored video signals.

4AA target-identifying circuit for use in beacon systems comprising, incombination:

a plurality of shift registers connected in series, the

first of which receives the received video signal as 1 an input, anoutput being taken from the last stage of each shift register so thatthere are a plurality of parallel outputs; and

decoding means comprising a plurality of AND and OR-gates arranged in aPascal triangle wherein the number of levels is equal to the number ofshift reg isters, each level being associated with a different shiftregister and having as inputs the output of its associated shiftregister, the inverse of the shifteach level comprising a number ofAND-gates horizontally arranged with all but the end AND-gates arrangedin output pairs, each pair feeding into an OR-gate, the outputs of thatlevel consisting of the outputs from the two end AND-gates and the OR-gates,

the outputs from the lowest-level end AND-gates and OR-gates beingm-out-of-n-occurrence indicating signals, where n is equal to the numberof shift registers plus one, and m is a number selected from the group 0to n.

S. A circuit as in claim 4, further outputs being taken from each endAND-gate at the right side of the Pascal triangle to provide signalswhich indicate runs of logical ones in the received video signal andoutputs being taken from each end AND-gate at the left side of thePascal triangle to provide signals which indicate runs of logical zeroesin the received video signal.

1. A target-identifying circuit for use in beacon systems comprising:storage means for chopping each interrogation period into a plurality ofsmall range-bin periods and for providing a plurality of simultaneousoutputs for each range-bin period comprising the signal received forthat range-bin period during the immediate interrogation and apredetermined number of previous interrogations, said simultaneousoutputs being derived in order for each range-bin period in theinterrogation period and the whole process being repeated for eachinterrogation period; and decoding means arranged in the form of aPascal''s triangle for classifying the incoming video signals by anm-out-of n classification where n is the predetermined number of bitpositions in the word to be analyzed, corresponding to the number ofsimultaneous storage means outputs plus one, and m is the number of truebits which occur in the word, corresponding to a number from zero to n.2. A circuit as in claim 1, further providing outputs indicating runs ofconsecutive logical ones in the incoming and stored video signals.
 3. Acircuit as in claim 1, further providing outputs indicating runs oflogical consecutive zeros in the incoming and stored video signals.
 4. Atarget-identifying circuit for use in beacon systems comprising, incombination: a plurality of shift registers connected in series, thefirst of which receives the received video signal as an input, an outputbeing taken from the last stage of each shift register so that there area plurality of parallel outputs; and decoding means comprising aplurality of AND and OR-gates arranged in a Pascal triangle wherein thenumber of levels is equal to the number of shift registers, each levelbeing associated with a different shift register and having as inputsthe output of its associated shift register, the inverse of theshift-register output and the outputs of the level above it, except thatthe first or topmost level has as inputs the incoming video signal andits inverse in place of the outputs of the level above it, each levelcomprising a number of AND-gates horizontally arranged with all but theend AND-gates arranged in output pairs, each pair feeding into anOR-gate, the outputs of that level consisting of the outputs from thetwo end AND-gates and the OR-gates, the outputs from the lowest-levelend AND-gates and OR-gates being m-out-of-n-occurrence indicatingsignals, where n is equal to the number of shift registers plus one, andm is a number selected from the group 0 to n.
 5. A circuit as in claim4, further outputs being taken from each end AND-gate at the right sideof the Pascal triangle to provide signals which indicate runs of logicalones in the received video signal and outputs being taken from each endAND-gate at the left side of the Pascal triangle to provide signalswhich indicate runs of logical zeroes in the received video signal.